In compliance with demand for low profile electronic products, such as notebook (NB), personal digital assistant (PDA), or set top box, besides improvement in component integration technology, internal components thereof are also preferably dimensioned with reduced volume, thickness or weight. Therefore, for a semiconductor package, which is a core component of an electronic product, it has been endeavored in the art to effectively reduce height and size of the semiconductor package.
Profile miniaturization for semiconductor packages is effected as developing from a leadframe-based package to a BGA (ball grid array) package, and further to a chip scale package (CSP). However, such a CSP still has significant drawbacks. First, in the CSP, a chip is electrically connected to a substrate by bonding wires that extend radially from a periphery of the chip to the substrate, thereby making size of the CSP hardly reduced in consideration of height of wire loops and area on the substrate occupied by the bonding wires. Moreover, if a flip chip is adopted in the CSP for electrically connecting the flip chip to the substrate by means of solder bumps, overall height of the CSP is still hardly reduced by combining heights of the flip chip, solder bumps, substrate and solder balls implanted beneath the substrate. And, the use of flip-chip technology would also undesirably increase costs and process complexity in fabrication. Further, provision of the substrate would increase overall structural height, and also fabrication costs of the CSP by taking account of relatively high costs in substrate manufacture. In addition, in the CSP, due to mismatch in coefficient of thermal expansion (CTE) among the chip, the substrate and an encapsulant that encapsulates the chip, thermal stress would be produced and applied on the chip, thereby causing warpage or delamination to the CSP during temperature variation in fabrication processes, a reliability test or practical use, which would adversely affect reliability and yield of fabricated products.
There is disclosed a semiconductor package without using a substrate in Taiwan Patent No. 16123 entitled “SEMICONDUCTOR PACKAGE WITHOUT CHIP CARRIER AND METHOD OF MAKING THE SAME”. This patent is characterized by forming an encapsulant for encapsulating both active and non-active surfaces of a chip in the semiconductor package, so as to provide desirable mechanical strength and protection for the chip, without having to use a chip carrier e.g. substrate. Such a package structure indeed effectively contributes to overall profile reduction; however, it is still inherent with significant drawbacks. For example, end portions of conductive elements mounted on the active surface of the chip, are flush with an exposed surface of the encapsulant formed on the active surface. When implanting conductive media e.g. tin balls, solder bumps or solder paste on the end portions of the conductive elements, during a solder-reflowing process, due to lack of an anchoring mechanism between the conductive media and the end portions, the conductive media may not be firmly held in position, but collapse or melt to contaminate adjacent conductive media; this leads to bridging or short circuit between conductive media, and the bridging effect may allow a conductive medium to be partly or completely absorbed by an adjacent conductive medium due to cohesion difference between the bridged conductive media. This makes the conductive media variably dimensioned in size or height, leading to incomplete electrical connection between the semiconductor package and an external device. Therefore, how to overcome the above problems for preventing conductive media for contacting or short-circuiting with each other, is now an important topic to endeavor.